Many computer systems include peripheral unites accompanying a core processor. Such a peripheral unit is a Direct Memory Access (DMA) controller.
Efficient memory access and management has been a subject for research and development for a long time. For example, U.S. Pat. No. 4,137,565 (published 1979, assigned to Xerox Corporation), incorporated herein by reference, discloses a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, and a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be incurred if the data were to be manipulated by a central processor in the central processing unit module.
Since then, efforts have been made to improve efficiency of memory access and management. For example, EP 1,026,596, incorporated herein by reference, (published 2000, in the name of SUN Microsystems, Inc.) discloses a direct memory access (DMA) controller for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer. The DMA controller is responsible for updating the tail pointer in the DMA controller in association with reading of a direct memory access command from a location in the command buffer. The processor is responsible for updating the head pointer in the DMA controller in association with the storing of DMA commands in the command buffer.
However, sometimes memory access requires accessing memory addresses that are not linear. This typically occurs, for example, in image processing. Accessing non-linear memory addresses is done, in most cases, by implementing multiple channels that require management and limit performance.
U.S. Pat. No. 6,108,743, incorporated herein by reference, (published 2000, assigned to Intel Corporation and Real 3D Inc.) discloses a method for performing direct memory access, which includes arbitrating between a chained, low priority, direct memory access and a high priority, direct memory access, the arbitration occurring between two links in the chained, low priority, direct memory access.
In the field of memory access in image processing U.S. Pat. No. 6,449,664, incorporated herein by reference, (2002, assigned to ViewAhead Technology, Inc) discloses a two-dimensional direct memory access system that maximizes processing resources in image processing systems. The system disclosed in U.S. Pat. No. 6,449,664 includes a two-dimensional direct memory access machine and a ping-pong style memory buffer to assist in the transfer and management of data, such as image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor.
U.S. Pat. No. 5,579,453, incorporated herein by reference, (published 1996, assigned to Xerox Corporation) discloses a smart direct memory access controller for data space transformation. The smart direct memory access controller can be used in computer systems to read and/or write data in a non-linear fashion in order to alter the organization of data stored within the computer system. The direct memory access controller has particular application in the electronic subsystem of a non-raster format electronic printer, such as a partial width array or full width array thermal ink jet printer. The smart direct memory access controller enables a non-raster format printer to access images organized in raster format, by viewing the data space as a non-linear or multi-dimensional memory. Memory addresses of the non-linear or multi-dimensional address space are a catenation of several data fields. Each field is one of the coordinates that define the location of data within memory. In the smart direct memory access controller any one or more of the fields can increase when it comes time to increment the address, giving rise to data streams that are actually vectors through the data space.
U.S. Pat. No. 6,260,081, incorporated herein by reference, (published 2001, assigned to Advanced Micro Devices, Inc.) discloses a direct memory access engine that supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.